The efficiency of a conventional switched power converter, such as a buck converter, is dominated by the losses within the switches (e.g. field effect transistors, FETs) and the inductor of the power converter. If the power converter provides a relatively high output voltage Vout, the power converter typically exhibits a reduced conversion efficiency, because the switches must be implemented in high voltage technology, and thus the switches have an increased switch area and increased reverse recovery losses. Relatively large FETs typically cause relatively high switching losses, because of an increased gate charge and LX capacitance.
The voltage which is applied to the inductor of a buck converter is proportional to the difference between the input voltage Vin and the output voltage Vout, i.e. Vin−Vout, during the magnetization phase, or proportional to Vout during the demagnetization phase. Increased inductor voltages cause increased current variations dI/dt and thus an increased switching frequency (for achieving a pre-determined current ripple) and/or an increased current ripple (for a given switching frequency). In both cases this leads to increased inductor core losses and to an increased dissipation power.
Maintaining low current variations dIL/dt at increased input and output voltages typically requires inductors (i.e. coils) with increased inductance L, due to the relation dIL/dt=VL/L. However, coils with an increased inductance L have an increased number of turns. For inductors to maintain their Direct Current Resistance (DCR) even with an increased number of turns, each turn has to make use of a wire with an increased thickness to compensate for the impedance increase. Thus the size of the inductor is growing twice with an increased inductance L (due to the increased number of turns and due to the increased wire thickness). On the other hand, if the inductor dimensions are not increased, an increased inductance L leads to the effect that the DCR of the inductor is growing twice due to the additional number of turns and due to the use of a thinner wire.
Over the last years, battery powered applications such as smartphones and tablets increased their computing power, screen resolution and display frame rate and added connected standby modes. This triggered changes in the requirements for the power management of such battery powered applications.
The increased computing power triggered a growth in maximum current requirements. The trend towards higher peak currents was accelerated by the ongoing shrink of technology nodes. Processor cores may now exhibit millions of transistors on a single chip. But the smaller geometries increase leakage currents from each transistor with the result that modern multi-core processors implement leakage current in the range of Amperes.
Typical processors of early smartphones were continuously in active mode, whenever the smartphone was in use, scaling the provided computing power by changing the processor's clock rate (and supply voltage) depending on the MIPS demand (pulling an average current in the range of 1-2 A). On the other hand, todays processor cores are either running at maximum speed or are disconnected from a power rail to reduce the leakage current of a processor core to a minimum duty cycle. The provision of the required MIPS within short duty cycles leads to a substantial increase of the processor's peak current consumption (by a factor of more than 10), while the battery capacity and the thermal handling capability of such portable applications have increased at a slower rate. As a result of this, the provision of peak currents is typically limited to relatively short periods and by that has limited impact on the average current consumption of the battery powered application.
In multi-core topologies only a subset of available cores are enabled in order to provide sufficient processing power to handle a required computing load. Furthermore, “Big-Little” architectures may be provided, which use smaller processor cores during normal usage, and which flip transparently to more powerful cores when detecting a user command, during screen update or after application wake-up.
The total heat-up and thermal limit of a battery powered application is typically dominated by dissipation power of the IC consuming the peak power (80-90%), so that in most cases the efficiency of the power supply of a battery powered application is less important during peak current events.
The introduction of so called “Connected Standby Modes” disabled the complete shutdown of a battery powered application. Smartphones or Tablets are nowadays continuously processing Email, Social Network Data, News Feeds, GPS and other sensor output in the background. This is implemented in dedicated low power modes, so that the drain of the battery is minimized. In these modes the dissipation power of the power supply typically has a substantial impact on the mobility time of a battery powered application. As such, there is a need for increasing the efficiency of power converters at light loads.
Where in former times a battery powered application was either in use or put to a deep standby mode (with only the wireless modern periodically waking up to check the network connection) todays battery powered applications are most of the time in a light load mode (pulling a few mA), but can also pull significant short term peak currents up to 20 A to implement short application response times by enabling maximum computing power for limited periods of time.